The comprises invention alone and in combination the setting and control of data packet buffer thresholds as delimited in one or more counters within a station, and includes limits to the rate of request to send data packets and limits to the total number of packets issued by a station. In brief, counters and limits (thresholds) on counters, and queues and limits (thresholds) on queues, are used to control transmission (for example, transmission rate) processes on the bus communications medium.
Another environment in which this invention may be applied is the interaction between the Central Processing Unit (CPU) of a computer and the Peripheral Interface Adaptor (PIA) and/or any other component attached which are required to contend for access on to a high speed computer bus architecture utilising any length or speed digital data packet transfer communications medium.
The invention is also applicable to a wide variety of other digital data transfer environments allowing for partial or full implementation of the mechanism, since partial and full application of the mechanism provides different advantages, problem elimination and economies of operation for each of the applicable environments.